1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the invention relates to a semiconductor device in which a short-circuit between gate interconnections and bit lines caused by a dummy pad contact formed at an end of memory cells using a self-alignment method is avoided, and to a method of manufacturing a semiconductor device in which a step produced between memory cells and their peripheral portions can be eliminated by forming and polishing a dummy pad contact at the end of memory cells.
2. Description of the Background Art
In recent years, the degree of integration of semiconductor devices has been enhanced and memory cells have been reduced in size, so that it has been difficult to form contacts in the gap between interconnections only by photo-resist masking without short-circuiting the interconnections. One of the methods used for forming contacts in gaps of interconnections without short-circuiting is a so-called self-alignment method. FIG. 28 shows a sectional view of a pad contact hole opened in an interlayer oxide film using this self-alignment method. In FIG. 28, a silicon interconnection 902 which comes to be a gate interconnection is formed on a semiconductor substrate 910 with an insulating film 901 interposed, and is coated with nitride layers 903, 904. On an interlayer oxide film 905 deposited on these layers, a pad contact hole 915, where a pad contact is formed for conducting an active region 911 and a top layer portion, is opened.
The self-alignment method in general is now described in order. First, a silicon interconnection is deposited on a semiconductor substrate with an insulating film interposed. A nitride film protecting the silicon interconnection is then formed on the top and the side surfaces of the silicon interconnection. In this step, the silicon interconnection comes to be coated with the nitride film. Thereafter, an interlayer oxide film is deposited and then the interlayer oxide film is etched to open a contact hole using a photoresist mask on a desired position. When the interlayer oxide film is etched with selective ratio of the oxide film (i.e., the interlayer oxide film) to the nitride film being greater than prescribed value, the silicon interconnection can be protected from etching, by the nitride film on the top and the side surfaces. Thus, if the opening diameter of pad contact hole 915 is larger than the interval between silicon interconnections, as shown in FIG. 28, the opening diameter would be overlapped with the silicon interconnections. No short-circuit occurs, however, as the silicon interconnection is protected by the nitride layer. Therefore, as shown in the sectional view of FIG. 29, the nitride films 903, 904 on the top and the side surfaces of the silicon interconnections are left with a sufficient thickness, even when the pad contact hole 915 is opened. With this method, the pad contact can be formed without short-circuiting the silicon interconnection and the pad contact.
On the other hand, from the reason described in the following, at end portions of memory cells, a dummy pattern such as a dummy pad contact is generally provided. Since the continuity (repetition) of the pattern is lost at the end of the memory cells, the pattern at the end-most portion, especially the contact diameter, is reduced due to an optical proximity effect. To dissolve this inconvenience, a dummy contact is provided around a body of the memory cells. By providing the dummy contact, though the dummy contact diameter becomes small due to an optical proximity effect, the memory cell body contact formed inner than the dummy contact can have an intended size. In this case, it is very difficult to control the size of the pattern in the end-most portion. For example, even when the size of the mask is set a little larger than that of the pad contact in the memory cell, the diameter of pad contact 921 at the end may possibly be oversized, resulting in short-circuiting with adjacent pad contact 920 positioned inside. In FIG. 30, there is also shown an arrangement of a gate interconnection 930 and another pad contact (the second pad contact) 906 on which a bit line contact is formed. In the following description, pad contact 906 formed overlapped with the bit line when viewed two-dimensionally will be referred to the second pad contact, and is distinguished from pad contact 921 (the first pad contact) formed between the bit lines. Furthermore, in particular, when referred simply as xe2x80x9ccontactxe2x80x9d or xe2x80x9cpad contactxe2x80x9d, it will include both pad contacts.
Thus, as it is difficult to control the size of the pad contact at the endmost portion, as shown in FIG. 31, a mask opening 924 of the first pad contact in the dummy and a mask opening 925 of the first pad contact of the memory cell body are normally formed to have the same size. In FIG. 31, there is also shown a mask opening 926 for the second pad contact 906. As a result of setting mask opening 924 of the first pad contact in the dummy, the diameter of first pad contact 921 of the dummy becomes smaller than that of first pad contact 920 of the cell body, as shown in FIG. 32.
The above-described self-alignment method has the following problems. When a contact hole is opened using the self-alignment method and the hole diameter of the photo-resist to be an etching mask is small, the tip portion of the etching gas opening the interlayer oxide film will not contact in wide area with the nitride film on the top and side of the interconnection. When the etching gas contacts in wide area with the nitride film coating the interconnection, the etching selective ratio of the oxide film (i.e., the interlayer oxide film) to the nitride film is high in etching so that the etching gas will not much etch the nitride film. The reason for this is as follows: C4F8, C5F8, CH2F2 and so forth are used as etching gas species, and these plasma gas etch the interlayer oxide film and the nitride film while depositing a film of polymer including C on the nitride film. Thus, when the contact area between the nitride film of the gate interconnection coating and the etching gas is wide, the nitride film is etched while the sufficient deposition film being deposited. When only a corner of the gate interconnection coating and the etching gas contacts, however, the deposition does not much proceed while the etching only proceeds. Therefore, when the diameter of the contact hole is small, the etching selective ratio of the oxide film to the nitride film in the etching will be low. At the end portion of the memory body, the diameter of the contact hole becomes smaller due to an optical proximity effect, so that the etching selective ratio of the oxide film to the nitride film on the etching will be low. Thus, if the dummy pad contact is formed at the end of the memory cells using the self-alignment system, the remaining nitride film will be thinner as shown in the circle A in FIG. 33. Therefore, at the step in which the nitride film at the contact bottom is eliminated, the interconnections are exposed at the top and the side wall of the interconnections, as shown in the circle B in FIG. 34. As a result, filling a plug to form a pad contact causes short-circuit with the pad contact.
Today, as the sizes of semiconductor devices and contacts thereof are more and more being reduced, the frequency of such short-circuits tends to be increasing. In the case of a contact in a memory cell body, a mask opening may be so provided as to enable the etching gas to somehow contact in a wide area with the nitride film on top and side wall portions of the interconnections. With respect to a dummy pad contact which is smaller in size due to an optical proximity effect, however, the contact area with the nitride film is smaller so that the nitride film is, in fact, easily eliminated by etching. Thus, when a pad contact is formed between gate interconnections using the self-alignment method, the first dummy pad contact being smaller in size has higher possibility of short-circuiting with the gate interconnections. FIG. 35 is a plan view of an end portion of a memory cell showing the first dummy pad contacts 921 formed at the end portion of the memory cell. The diameter of first dummy pad contact 921 formed at the end portion of the memory cell is smaller than that of the first pad contact 920 of the inner memory cell body. In FIG. 35, bit line 908 is conducted with an active region via a bit line contact 909 and the second pad contact 906. FIG. 36 is a sectional view taken along line XXXVIxe2x80x94XXXVI of FIG. 35. As shown in FIG. 36, if first dummy pad contact 921 was short-circuited with gate interconnection 902 at section B, the short- circuited gate interconnection 902 would be conducted with bit line 908 via active region 911. As a result, the electric potential of bit line affects that of the gate interconnection, causing malfunction of the device. Thus, the structure and the size of the first dummy pad contact have come to present such problems that were previously not experienced, because the self-alignment method is used for opening and forming contacts.
Further, aside from the above, the following problem arises in connection with a boundary portion of a memory cell area and a peripheral area thereof. FIG. 37 shows an arrangement of various portions of an end portion of a memory cell. FIG. 38 is a sectional view taken along line XXXVIIIxe2x80x94XXXVIII of FIG. 37, showing a structure in which an inter-layer insulating film is formed. It is understood that an inter-layer insulating film 905, formed across both regions of the memory cell and its peripheral portion, reflects the under-layer structure, so that the inter-layer insulating film of the memory cell is positioned higher than that of the peripheral area thereof, resulting in a step at the boundary portion 950. The step C could not be eliminated by polishing through CMP(Chemical Mechanical Polishing) method, as shown in FIG. 39. This causes variation in sizes of bit line contact and a photo-resist of the bit line of upper layers.
An object of the invention is to provide a semiconductor device with a structure in which no short-circuit occurs between dummy pad contacts and gate interconnections when dummy pad contacts are formed at an end portion of a memory cell, or semiconductor device with a structure in which bit lines would not affect the electric potential of gate interconnections even if a short-circuit occurred between the dummy pad contacts and the gate interconnections. Furthermore, another object of the invention is to provide a method of manufacturing a semiconductor device, in which no large steps are produced on an inter-layer insulating film in the vicinity of an end-portion of a memory cell.
According to one aspect of the invention, a semiconductor device includes a semiconductor substrate, an active region formed by introducing an impurity onto a main surface of the semiconductor substrate, a gate interconnection deposited on the main surface of the semiconductor substrate with an insulating layer interposed, a gate interconnection coating formed of a nitride film protecting the gate interconnection, a bit line formed above the gate interconnection crossing the gate interconnection when viewed two-dimensionally, and an inter-layer oxide film covering the main surface of the semiconductor substrate and the gate interconnection coated by a gate interconnection coating. The semiconductor device further includes a memory cell having a first pad contact formed, penetrating through the oxide film, between the gate interconnection and the bit line, when viewed two-dimensionally, and conducting the active region and the upper-layer portion, and a second pad contact formed, penetrating through the oxide film, overlapped with the bit line, when viewed two-dimensionally, between gate interconnections, conducting the active region and the bit line via a bit line contact. The semiconductor device further includes first dummy pad contacts formed between gate interconnections, using a self-alignment method, along with an end portion of a memory cell in a dotted line, and means for interrupting an electric conduction occurred between the first dummy pad contact and the bit line somewhere in a path leading from the first dummy pad contact through the active region, the second pad contact and the bit line contact all the way to the bit lines.
This arrangement prevents the serial conduction of the path leading from the first dummy pad contacts to the bit lines. Thus, no short-circuiting would occur, even when the first dummy pad contacts formed at an end portion of a memory cell comes to have smaller size because of an optical proximity effect, and as a result, an etching selective ratio of the oxide film (i.e., inter-layer insulating film) to a nitride film becomes smaller in etching and the nitride film is eliminated or formed extremely thin. Thus, the potential of the bit line would not affect that of the gate interconnection, even if any one of the first dummy pad contacts arranged in a dotted line is short-circuited with the gate interconnection. The bit line of the above-described semiconductor substrate may be a bit line provided in a memory cell body. Alternatively, it may be dummy bit lines provided in order to form bit lines in the body side of an intended size. Furthermore, bit lines can be both of the above. As a constant potential is applied to the dummy bit line, when a short-circuit occurs, the influence of the dummy bit line on the potential of the gate interconnection is larger than that of the bit line of a memory cell body.
According to one aspect of the invention, the above-described conduction is blocked when, for example, the first dummy pad contacts arranged in a dotted line are all formed on a region other than the active region of a main surface on a semiconductor substrate so as to cut-off the electric conduction between the first dummy pad contacts and the active region. In this case, it is desirable that the region other than the active region is the region of an isolating insulating film.
Because the above-described arrangement cuts-off the electric conduction between the first dummy pad contact and the active region, the potential of the bit line will not affect the electric potential of the gate interconnection.
Furthermore, in order to form the first dummy pad contacts at the end-most portion of a memory cell on the isolating insulating film in a dotted line, it is desirable to form the first dummy pad contacts in two dotted lines at an end portion of a memory cell, with the first dummy pad contacts at the end-most line of the memory cell being arranged on a region of the isolating insulating film in a dotted line.
Such arrangement ensures opening of the first dummy contact holes of the outer-most line on the isolating insulating film. As a result, no problems will be caused, even if the size and the selective ratio of an oxide film to a nitride film are reduced when opening the first dummy pad contact holes in the out-most line, and the first dummy pad contacts and the gate interconnections are short-circuited due to the loss or the thinness of the nitride film. Therefore, the conduction between the first dummy pad contacts and the active region of the main surface on the semiconductor substrate will not occur, and the potential of the gate interconnection would not affect that of the bit line.
In another example in which the above-described conduction does not occur, a bit line may be formed detouring a bit line contact to avoid an electric conduction between the bit line contact and the bit line. This arrangement also prevents the influence on the potential of the gate interconnection, caused by that of the bit line.
Another example in which the above-described conduction does not occur is that the first dummy pad contacts are formed within the inter-layer oxide film and not reaching the gate interconnection coating, cutting off the electric conduction between the first dummy pad contact and the active region. The bit line contact may be formed within the insulating film, not penetrating the insulating film formed on the above-said inter-layer oxide film, cutting off the electric conduction between the bit line contact and the second pad contact.
A semiconductor device according to another aspect of the invention includes a semiconductor substrate, an active region formed on a main surface of the semiconductor substrate with an impurity introduced, a gate interconnection deposited on a main surface of the semiconductor substrate with an insulating film interposed, a gate interconnection coating formed of a nitride film, which encloses and protects the gate interconnection, a bit line formed above the gate interconnection crossing the gate interconnection when viewed two-dimensionally, and an inter-layer oxide film covering the main surface of the semiconductor substrate and the gate interconnection coated with the gate interconnection coating. The semiconductor device also includes a memory cell having a first pad contact formed, penetrating through the oxide film, between the gate interconnection and the bit line, when viewed two-dimensionally, conducting the active region and the upper-layer conducting interconnection, and a second pad contact formed, penetrating the inter-layer oxide film, overlapped with the bit line, when viewed two-dimensionally, between gate interconnections, conducting the active region and the bit line via a bit line contact. The semiconductor further includes first dummy pad contacts formed between gate interconnections, using a self-alignment method, along with an end portion of a memory cell in a dotted line, the interconnection coated with a gate interconnection coating having an extended width, when viewed two-dimensionally, at the end portion of the memory cell where the first dummy pad contacts are provided.
When a contact hole for the first dummy pad contact is formed, the size of the contact area between etching gas and a nitride film, which is a protective layer for the gate interconnection, is enlarged because of the above-described arrangement. This prevents reduction of the etching selective ratio of the oxide film (i.e., an inter-layer insulating film.) to the nitride film in etching. For this reason, etching of the nitride film (i.e., a gate interconnection coating) by larger amount can be avoided. As a result, the conduction between the first dummy pad contact and the gate interconnection will not occur, and the potential of the gate interconnection will not affect that of the bit line.
In a semiconductor device according to a further aspect of the invention, the effect of widening the gate interconnection at an end portion of the memory cell can be seen from the following examples. The first dummy pad contacts arranged in a dotted line all have more than a half of the lower end portions, not reaching the main surface of the semiconductor substrate, when viewed two-dimensionally. More than a half of the lower end portions contact with and stop at the top and side surfaces of the gate interconnection, and none of the first dummy pad contacts arranged in a dotted line conducts with the gate interconnections. This prevents the electric potential of the gate interconnections from influencing that of the bit lines, since no short-circuit occurs between the first dummy pad contact and the gate interconnection.
In the semiconductor device according to another aspect of the invention, all of the lower end portions of the first dummy pad contacts may contact with and stop at the gate interconnection coating layer which coats the gate interconnection.
The above-described arrangement prevents the reduction of the etching selective ratio of the oxide film to the nitride film in etching the oxide film, when the first dummy contact holes are formed. Thus the nitride film remains thick, and short-circuit between the first dummy contact holes and the gate interconnections can be avoided. For another reason from above, even if the short-circuit occurred between the first dummy pad contacts and the gate interconnections, the electric potential of the gate interconnections would not be influenced by that of the bit lines, as the first dummy pad contact does not reach the active region.
Further, in the semiconductor device according to a still further aspect of the invention, the gate interconnection coated with the gate interconnection coating preferably has its width increased at one side, when viewed two-dimensionally, to include the first dummy pad contact in the end portion of the memory cell where the dummy pad contacts are provided.
The above-described arrangement permits the tip of the first dummy pad contacts to be completely and securely held on the gate interconnection coating layer, even if the reduction in the size of the first dummy pad contacts or some misalignment in the contacts occurred. In a semiconductor device, where more than a half of the lower end portions of all the first dummy pad contacts contact with and stop at the gate interconnection coating on the top and the side of the gate interconnection and where the conduction between any of the first pad contacts and the gate interconnection is avoided, the gate interconnection coated with the gate interconnection coating is preferably made wider at both sides thereof to overlap with the first dummy pad contacts, when viewed two-dimensionally, at the end portions of the memory cell where the first dummy pad contacts are provided.
As described above, because of the gate interconnection widened at opposite sides at the end portion of the memory cell, the contact area between etching gas and the nitride film can be enlarged and the reduction of the etching selective ratio of the oxide film to the nitride film can be prevented. Thus, the progress of etching on the nitride film can be suppressed and short-circuit between the first dummy pad contacts and the gate interconnection can be prevented.
In the semiconductor device according to yet another aspect of the invention, the gate interconnection coated with the gate interconnection coating, formed at the end portion of the memory cell where the first dummy pad contact is provided, is preferably a dummy gate interconnection coated with the gate interconnection coating.
The dummy gate interconnection can be formed primarily for suppressing the progress of etching, better than the gate interconnection formed on the memory cell body, and yet eliminating possibility of short-circuit, depending on manufacturing processes.
A method of manufacturing a semiconductor device according to a yet further aspect of the invention includes the steps of forming a memory cell including an array of gate interconnections on a main surface of the semiconductor, forming an inter-layer insulating film over regions of a memory cell and the continuing peripheral region thereof, providing a dummy pad contact holes, each at a gap between a gate interconnection and a bit line, in a dotted line along an end portion of the memory cell, forming a plug at each dummy pad contact hole, and continuously polishing to planarize the inter-layer insulating film at the regions of a memory cell and the continuing peripheral region thereof.
When a dummy pad contact is not provided, the inter-layer insulating film usually becomes thicker at the memory cell body side and thinner at the peripheral portions thereof, causing a large step around that portion. If the step portion is polished after providing the dummy pad contact as described above, however, the area contacting with the polishing cloth at the end portion of the memory cell is reduced and the polishing rate at the memory cell body side is increased, allowing elimination of the step. It is preferable that the polishing is performed by the CMP (Chemical Mechanical Polishing) method because, it can easily attain the high degree of flatness.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.